It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area as well as the number of interconnect levels are increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the interlayer dielectric (ILD) materials used to electrically insulate metal lines. As a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays.
State-of-the-art semiconductor chips employ copper (Cu) as the electrical conductor and inorganic organosilicates as the low dielectric constant (low k) dielectric, and have up to twelve levels of Cu/low k interconnect layers. These Cu/low k interconnect layers are fabricated with an iterative additive process, called dual damascene, which includes several processing steps including, for example, film deposition, patterning by lithography and reactive ion etching, liner (Cu barrier) deposition, Cu metal fill by electrochemical plating, and chemical-mechanical polishing of excessive Cu metal; these steps are described in greater detail in the following paragraphs.
When fabricating integrated circuit wiring within a multi-layer interconnect scheme, an insulating or dielectric material, e.g., silicon oxide or a low k insulator will normally be patterned with at least several thousand openings to create conductive line openings and/or via openings using photo patterning and plasma etching techniques, e.g., photolithography with a photoresist subsequently followed by etching by plasma processes. These via and line openings are typically filled with a conductive metal material, e.g., aluminum, copper, or their alloys etc., to interconnect the active and/or passive elements of the integrated circuits. The semiconductor device is then polished to level its surface.
A continuous cap layer is then normally deposited over the planarized surface featuring the dielectric material and conductive metal material. Next, a dielectric material is deposited over the continuous cap layer, via and conductive line openings are created again within the dielectric layer as before, another conductive metal material is deposited within the openings and another continuous cap layer is deposited thereon. The process is repeated to fabricate a multi-layer interconnect wiring system. The multi-layer interconnect system built thereby is referred to in the art as a dual damascene integration scheme.
Unfortunately, the strategy to introduce low k materials (typically dielectrics whose dielectric constant is below that of silicon oxide) into advanced interconnects is difficult to implement due to the new materials chemistry of the low k materials that are being introduced. Moreover, low k materials exhibit fundamentally weaker electrical and mechanical properties as compared to silicon oxide. Further, the patterned dielectric alternatives are typically susceptible to damage during the various interconnect processing steps. The damage observed in the low k materials is manifested by an increase in the dielectric constant and increased moisture uptake, which may result in reduced performance and device reliability.
Optical lithography has been the workhorse to continuously shrink (or scale) semiconductor devices and their related interconnect structures. Traditional scaling by optical lithography has been achieved with one single exposure mostly by reduction in the wavelength of the light sources, new tool design (higher numerical aperture or NA), improved lithographic materials or a combination thereof. Recently, multiple patterning, particularly double patterning techniques, where one particular level of circuitry is patterned by exposing the wafer to the light sources using two mask sets, has become increasingly necessary to maintain the pace of scaling at 193 nm optical wavelength. This type of double patterning necessitates significantly increase in complexity and the attendant increased manufacturing costs. Furthermore, this type of double patterning requires precise placement of the second exposure over the patterns formed by the first exposure. Any imperfect placement, or mis-alignment or overlay error, can cause degradation in performance or reliability or both. Such mis-alignment is due to the limitation of the lithographic tool employed or processing errors.
One way to overcome the integration challenges of low k materials mentioned above is to protect low k materials by adding at least one sacrificial hardmask layer onto a surface of the low k material. While the hardmask layer serves to protect the low k material, the presence of the sacrificial hardmask layer adds enormous process complexity and manufacturing as additional film deposition, pattern transfer etch, and removal of the hardmask layers are needed.
A state-of-the-art back-end-of-the-line (BEOL) integration process, called a low temperature oxide (LTO) process, employs up to eight layers of sacrificial hardmask materials to fabricate a two-layer dual damascene interconnect structure.
For example, a via-first LTO integration for forming a dual damascene interconnect includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one via in the dielectric material, such that at least one of the vias is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the via; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one trench in the imaging material, barrier material and planarizing material, such that the at least one trench is positioned over the via; removing the imaging material, either after or concurrently with forming the trench in the planarizing material; transferring the at least one trench to the dielectric material, such that at least one of the trenches is positioned over the via; removing the barrier material, either after or concurrently with transferring the at least one trench to the dielectric material; and removing the planarizing material.
A line-first LTO integration for forming a dual damascene interconnect structure includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one trench in the dielectric material, such that the at least one trench is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the trench; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one via in the imaging material, barrier material and planarizing material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the imaging material, either after or concurrently with forming the via in the planarizing material; transferring the at least one via to the dielectric material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the barrier material, either after or concurrently with transferring the at least one via to the dielectric material; and removing the planarizing material.
The prior art dual damascene integration schemes, such as the LTO one mentioned above, are very complex, inefficient, and costly. For example, the via-first LTO integration scheme requires ten layers of films and twenty-one process steps to form a two-layer dual damascene dielectric structure. In other words, 80% of the films are not needed in the final interconnect structure.
Although immensely popular in semiconductor manufacturing, the prior art dual damascene integration scheme described above suffers from several drawbacks including, for example, First, it constitutes a significant portion of manufacturing cost of advanced semiconductor chips as many layers, up to twelve layers for the state-of-the-art chips, are required to connect the minuscule transistors within a chip and to the printed circuit board. Second, it is a main yield detractor as the many layers of films required to form the interconnects generate chances for defect introduction and, thus, degrade manufacturing yields. Third, it is very inefficient and embodies enormous complexity. The current dual damascene integration scheme requires many sacrificial films (80% of the film stack) to pattern and protect the fragile interlayer dielectric films from damage during processing. These sacrificial patterning and protective films have to be removed after patterning and copper plating. Fourth, the performance gain by introduction of new lower-k materials is often offset by the need for higher-k non-sacrificial protective materials, such as a cap layer, a hardmask layer, or a thicker copper barrier layer. Fifth, the prior art complex dual damascene process lengthens manufacturing turn-around time and R&D development cycle. Sixth, the plasma etching process is an expensive and often unreliable process and requires significant up-front capital investment. Seventh, the aforementioned mis-alignment during double exposure, double patterning can cause degradation in performance and reliability of the resultant chips.
In view of the above, there is a need to simplify the formation of double patterned interconnects, including dielectrics for improved performance, reliability, cost-saving and manufacturing efficiency without mis-alignment as in the case with a traditional double exposure patterning scheme.